|
Section: Freelance programmers and web programmers resumes
Specialization: VHDL,Verilog,RTL,Assembly,IC Layout,PCB Layout Design
Experience: 3 years and 4 months
Age: 26 years
Sex: Male
Contact info:
First, Last name: Vipul Kumar
Phone: 91-9312005574
E-mail: er.vipulrajput@gmail.com
Full description:
VIPUL KUMAR
E-74 Siddarth Nagar, Ashram, Delhi.
Phone: +91-9312005574, +91-9911247932
E-mail: vipul_mbd23@yahoo.com
Summary
• 3 years and 4 months experience in HDL Design, Verification, Synthesis, FPGA based designs, IC Layout Design, 8051 Microcontroller, Circuit & PCB Design and EDA Tools.
• Knowledge of Digital Design, VHDL, Verilog, FPGA Architectures, HDL simulation & synthesis, ASIC design flow, STA, MOS physics, CMOS, DFT, Low Power Design, SOC, ARM Processor, 8051 Microcontroller.
Professional Experience
1) EFY Enterprises Pvt. Ltd.
EFY is ISO 9001:2000 Certified company and publishes umpteen numbers of Magazines (Electronics for You, Linux for You, Facts for You, BenefIT, Electronics Bazar), Books, Directories and Databases. Company also deals in electronic products and components through Kits 'n' Spares. EFY TechCenter provides hands-on training on latest technologies.
Designation: Application Engineer (VLSI-ESD)
Duration : 26th October 2009 to till date
Profile:
• FPGA and CPLD Logic Design using VHDL & Verilog HDL.
• Simulation, Synthesis & Implementation of FPGA based designs.
• IC CAD Designing using Tanner Tools.
• To develop Embedded firmware and testing using 8051 Microcontroller.
• To provide training on PCB & Circuit Design using Altium Designer & NI-Circuit design suite, PCB fabrication for basic circuits.
• To work closely with R&D team, and help them to reduce project development time.
• Training, Seminar, Workshop, Roadshows and Presentations on different technologies.
• Responsible for technical content writing and articles.
2) Trident Techlabs Pvt. Ltd. Delhi
Trident Techlabs, a forerunner in the field of Computer Aided Design provides world class technology for electronic design solutions. Techlabs is channel partner of Mentor Graphics, Aldec, Synplicity, Tanner EDA, Altium designer, Nu Horizons, National Instruments, Oasis Technologies, Visual Solutions and other companies. Company also provides Power consulting Services and Design services with different divisions.
Designation: Application Engineer (EDA)
Duration : From 3rd Oct. 2007 to 23rd Oct. 2009
Profile:
 Interface with customers to review their tool requirements, present and demonstrate EDA Tools solutions, and train them on the use of our tools.
 Responsible for the timely resolution of customer issues and evaluating and forwarding tool enhancement requests into R&D.
 To develop specific applications for clients and help them in their projects development related to VLSI Design, Circuit & PCB Design.
 Installing, configuring and testing of our solution at customer facilities.
 Seminars, Workshops and Benchmarks on EDA Tools and current technologies.
Seminar, Workshop & Assignments:
 Trained on Altium Designer6 (A Unified Electronic Product Development System) in Bangalore by Altium Limited Australia.
 Technical Demonstration of Aldec products in International Conference Altera SOPC World 2008 as a partner of Altera, in New Delhi.
 Developed first module (NMOS) with their own specifications (DRC setup, Technology setup, Layers) using Tanner Tools (L-Edit Pro) for Solid State Physics Laboratory (SSPL), DRDO Delhi.
 Workshop on “Leading Edge Verification Techniques using Aldec Active-HDL mixed language simulation for FPGA designs” at Instruments Research & Developments Establishment (IRDE), DRDO Dehradun.
 Seminar on “Role of EDA Tools in Circuit & PCB Design” at National Thermal Power Corporation (NTPC R&D) Greater Noida.
 Seminar on “FPGA Design Challenges” at Laser Technology (LASTEC), DRDO Delhi.
 Seminar on “VHDL based Critical Path Tracing Method for Fault Simulation” at Ambedkar Institute of Technology Delhi.
 Seminar on “MEMS Layout Designing Using Tanner Tools” at Semi-Conductor Laboratory (Department of Space) Chandigarh.
 3 Days Training on Altium Designer 2009(FPGA & Embedded Module along with Nanoboard-Altera CycloneII Daughter card) at Defense Electronics Application Laboratory DRDO Dehradun .
 Technical Demonstration of Mentor Graphics products (Modelsim, Questa, Precision Synthesis) in EDA Techforum 2009 at Noida.
Projects:
1. High speed ADC with VERTEXII FPGA development board.
Tools & H/W Used: ModelSim, XilinxISE, VertexII.
Developed a high speed ADC card with a Vertex-II. FPGA chip on board. This board is to be used for high speed ADC wherein certain algorithm implemented on that data and then either the data is stored or delivered to some other unit for further processing.
2. A complete soft processor based Video Display System on FPGA.
Tools & H/W Used: Altium Designer6, Nanoboard.
It is capable of capturing composite video and displaying the video on a touch screen, with options to scale and rotate the image. The TSK3000A is a host of peripherals that supply the means with which to both capture and display our video on the touch screen located on the desktop NanoBoard.
3. Design CMOS DRAM Memory cell.
Tools Used: Tanner Tools Pro (L-Edit, S-Edit, T-Spice, W-Edit, LVS).
It is implemented using CMOS 0.18-micron technology. It includes designing of CMOS cell to store data in form of bit and designing array of cells, Sense Amplifier, Row and Column Decoder. It is having refresh cycle of 5ms to 10ms.
3) Semiconductor Laboratory VEDANT, Lucknow U.P.
Designation : Design Engineer
Duration : From 15th June 2006 to 31st Aug 2007.
Projects:
1) VHDL implementation of BUS ARBITER.
Tools & H/W Used: ModelSim, Active-HDL, Xilinx ISE, Spartan3.
This project is based on Daisy Chaining method. There are three independent processors A, B & C and a common memory of 64 Kbytes processors share 64KB memory with priority. Time out is programmed through the independent processor and the data bus time period is 128 clock cycles.
2) VHDL implementation of Security System.
Tools Used: ModelSim, Active-HDL, Synplify-Pro, Xilinx ISE.
The designed ‘Security System’ detects that you are one of the authorized persons, who are permitted to enter the conference hall, otherwise you will be detected on your wrong entry by security system. Also be confirmed before entry that you are one of the first ‘n’ legal persons, because no further entries will be allowed into the hall after that ‘n’ entries & security system will block any further entry.
3) FPGA based Ultra Fast Multi channel scalar using Verilog.
Tools & H/W Used: Active-HDL, Xilinx ISE, Spartan2.
Developed a FPGA based Ultra Fast MCS i.e. multi channel scalar which works at 100 MHz and uses six counters one after the other to have zero dead time. We select the counters in turn to perform read and reset operation to achieve zero dead time. Wrote the code for FPGA Xilinx Spartan-2 in Verilog HDL. Tested the code on a Xilinx developer kit. Designed the ISA interfacing circuit and on board clock generators that are required to provide 100 MHz at a trigger. Downloaded the .bit file onto the manufactured board and verified the operation.
Technical Skills
Simulation Tools ModelSim 5.7 & 6.5, Active HDL 8.1, NC Sim, Multi HDL, Aldec Riviera, Questa.
Synthesis Tools Synplify Pro 8.9, Leonardo Spectrum, Precision Synthesis,
Cadence RTL Compiler, Synopsys FPGA Compiler, Xilinx
ISE and Chipscope pro.
Backend Design Tools Tanner Tools Pro (L-Edit, S-Edit, T-Spice, W-Edit, LVS-Layout Vs Schematic), Silvaco TCAD (Atlas, Athena)
PCB & Ckt Design Tools Altium Designer 6 (FPGA Module, Embedded Module, PCB design Module, Nanoboard), NI Circuit Design Suite (MultiSim, Multi MCU, UltiBoard), PADS
Other EDA Tools Timing Tool, NI LabVIEW (FPGA Module), KEILuV3, VissimComm6, Triton IDE.
HDLs/HVL VHDL, Verilog-HDL, Basic System Verilog
Language C, Assembly (8051, 8085)
Embedded H/W Oasis Titan Board (ARM7TDMI Development Platform)
Operating System Linux, Microsoft Windows
Educational Qualification:
P.G.D.I.T.: Pursuing Post Graduate Diploma in Information Technology from Symbiosis Center for Distance Learning Pune.
A.P.G.D. : Advanced Post Graduation Diploma (APGD) in VLSI design from VEDANT, Semiconductor Complex Ltd. (SCL), Mohali Chandigarh with 72% in Jan 2006.
B.Tech. : Electronics & Communication from U.P Technical University,Lucknow with 65% in June 2005.
12th : U.P. Board with 60%. ¬
10th : U.P. Board with 66%.
Training:
Organization : Central Electronics Limited Ghaziabad U.P.
Scope : Manufactured the universal axel counter for railways and
transducer in CEL and tested in System Production Division &
Quality Control Department.
Projects:
A.P.G.D Project: Design 8-Bit RISC Processor using Verilog-HDL.
Description: Processor is design to support 16 instructions with three addressing modes. Two-stage pipelining is used to execute one instruction per cycle and 12-bit instruction format to decode instructions. 16 internal registers are used to speed up register-to-register operations and only Simple LOAD and STORE operations accessing memory. One external Non-Maskable interrupt is also available.
B.Tech Project: Design of a Microcontroller for Paint Mixer Plant using VHDL
Description: A microcontroller is designed for the automation of the paint mixer plant using VHDL. Microcontroller controls the in-out motors of plant and stops the plant in any emergency and also controls the other functions of plant (like cleaning the furnace, level of furnace, mixing etc.).
Personality Traits: Lateral Thinking, Open to new Experience, Flexible Attitude
Curiosity and Learning.
Personal Details:
Date of Birth : 5th Aug 1983
Father’s Name : Shri Rohitashwa Kunwar
Permanent Address : Opposite Checkpost Tikonia
Thakurdwara, Dist: Moradabad
U.P. PIN: 244601
Hobbies : Singing & listening songs,
Versification.
Reference: Furnished on request
(VIPUL KUMAR)
|
